Specifications

Status Registers
10-28
10.5 Status Registers
The two status registers are the global status register (GSR) and the error sta-
tus register (ESR). As indicated by their names, GSR provides information for
all functions of the CAN peripheral and ESR provides information about any
type of error encountered.
10.5.1 Global Status Register (GSR)
Figure 10–18. Global Status Register (GSR) — Address 7107h
15–8
Reserved
7–6 543210
Reserved SMA CCE PDA Rsvd RM TM
R-0 R-1 R-0 R-0 R-0
Note: R = Read access; value following dash (–) = value after reset
Bits 15–6 Reserved.
Bit 5 SMA. Suspend Mode Acknowledge
0 The CAN peripheral is not in suspend mode.
1 The CAN peripheral has entered suspend mode.
This bit is set after a latency of 1 clock cycle up to the length of one frame after
the SUSPEND signal is activated.
Bit 4 CCE. Change Configuration Enable
0 Write access to the configuration registers is denied.
1 The CPU has write access to the configuration registers BCR while
CCR is set. Access is granted after reset or when the CAN module
reaches the idle state.
This bit is set after a latency of 1 clock cycle up to the length of one frame.
Bit 3 PDA. Power-Down Mode Acknowledge
Before the CPU enters its IDLE mode (to potentially shut off ALL device
clocks), it must request a CAN power down by writing to the PDR bit in MCR.
The CPU must then poll the PDA bit and enter IDLE only after PDA is set.
0 Normal operation.
1 The CAN peripheral has entered the power-down mode.
This bit is set after a latency of 1 clock cycle up to the length of one frame.