Specifications

CAN Control Registers
10-23 CAN Controller Module
Bits 15–14 Reserved
Bit 13 SUSP. Action on emulator suspend. The value of SUSP bit has no effect on the
receive mailboxes.
0 Soft mode . The peripheral shuts down during suspend after the
current transmission is completed.
1
Free mode . The peripheral continues to run in suspend.
Bit 12 CCR. Change Configuration Request
0 The CPU requests normal operation. It also exits the bus-off state
after the obligatory bus-off recovery sequence.
1 The CPU requests write access to the bit configuration registers
(BCRn). Flag CCE in the GSR indicates if the access is granted. CCR
must be set while writing to bit timing registers BCR1 and BCR2. This
bit will automatically be set to 1 if the bus-off condition is valid and the
ABO is not set. Thus, it has to be reset to exit the bus-off mode.
Bit 11 PDR. Power-Down Mode Request
Before the CPU enters its IDLE mode (if IDLE shuts off the peripheral clocks),
it must request a CAN power down by writing to the PDR bit. The CPU must
then poll the PDA bit in the GSR, and enter IDLE only after PDA is set.
0 The power-down mode is not requested (normal operation).
1 The power-down mode is requested.
Bit 10 DBO. Data Byte Order
0 The data is received or transmitted in the following order: Databyte
0,1,2,3,4,5,6,7.
1 The data is received or transmitted in the following order: Databyte
3,2,1,0,7,6,5,4.
Note:
The DBO bit is used to define the order in which the data bytes are stored
in the mailbox when received and in which the data bytes are transmitted.
Byte 0 is the first byte in the message and Byte 7 is the last one as shown
in the figure of the CAN message (Figure 10–4).
Bit 9 WUBA. Wake Up on Bus Activity
0 The module leaves the power-down mode only after the user writing a
0 to clear PDR.
1 The module leaves the power-down mode when detecting any
dominant value on the CAN bus.