Specifications

CAN Control Registers
10-22
If one or more RML bits in the RCR register are set, the RMLIF in the IF register
is also set. This may initiate an interrupt if the RMLIM bit in the IM register is
set.
RMPn: Receive Message Pending (for mailbox n)
If a received message is stored in a mailbox n, the bit RMPn is set.
The RMP bits can only be reset by the CPU and are set by the CAN internal
logic. The bits RMPn and RMLn are cleared by writing a 1 to the RMPn bit at
the corresponding bit location. If the CPU tries to reset a bit and the CAN tries
to set the bit at the same time, the bit is set.
A new incoming message will overwrite the stored one if the OPCn bit is
cleared. If not, the next mailboxes are checked for a matching identifier. When
the old message is overwritten, the corresponding status bit RMLn is set.
The RMP bits in the RCR register set the mailbox interrupt flag (MIFx) bit in
the IF register if the corresponding interrupt mask bit in the IM register is set.
The MIFx flag initiates a mailbox interrupt if enabled.
OPCn: Overwrite Protection Control (for mailbox n)
If there is an overflow condition for mailbox n, the new message is stored/
ignored depending on the OPCn value. If the corresponding bit OPCn is set
to 1, the old message is protected against being overwritten by the new mes-
sage. Thus, the next mailboxes are checked for a matching identifier. If no oth-
er mailbox is found, the message is lost without further notification. If bit OPCn
is not set, the old message is overwritten by the new one.
10.4.4 Master Control Register (MCR)
The Master Control Register is used to control the behavior of the CAN core
module.
Figure 10–14. Master Control Register (MCR) — Address 7103h
15–14 13 12 11 10 9 8
Reserved SUSP CCR PDR DBO WUBA CDR
RW-0 RW-1 RW-0 RW-0 RW-0 RW-0
7 6 5–2 1–0
ABO
STM Reserved MBNR[1:0]
RW-0 RW-0 RW-0
Note: R = Read access; W = Write access; value following dash (–) = value after reset