Specifications

Architecture Summary
2-2
2.1 Architecture Summary
The ’240x devices are implemented as ASIC customizable digital signal proc-
essors (cDSPs). The CPU, program ROM/FLASH is implemented as ASIC
hard macros as shown in the shaded blocks in Figure 2–1. The CPU uses the
LP256 hard macro which consists of the TMS320C2xx DSP CPU core, 544 x
16 words of dual-access RAM (DARAM), the analysis/JTAG logic, the internal
memory interface, and the logic interface. The logic interface, however, is not
used in the ’240x.
The peripherals interface to the internal memory interface of the CPU through
the PBUS interface. All on-chip peripherals are accessed through the periph-
eral bus, PBUS. At lower frequencies, all peripheral accesses (reads and
writes) are zero-wait-state, single-cycle accesses. All peripherals, excluding
the watchdog timer counter, are clocked by the CPU clock. A third ASIC
module is the 10-bit 500-ns A/D converter.
These devices have up to 41 bit-selectable digital I/O ports. Most or all of these
I/O ports are multiplexed with other functions, such as event manager signals,
serial communication port signals, or interrupts. Most of these multiplexed dig-
ital I/O pins come up in their digital I/O pin mode as an input following a device
reset. For a detailed description of the architecture and instruction set, refer
to the
TMS320C24x DSP Controllers CPU and Instruction Set Reference
Guide (SPRU160).
Figure 2–1. ’ 240x Device Architecture
C2xx CPU + JTAG
+ 544 x 16 DARAM
Mem I/F
Logic
I/F
P bus I/F
I/O
registers
ADC
control
CAN WD
SCI
ADC
P bus
Synthesized ASIC gates
ROM/flash
4K/8K x 16
SPI
Event
Managers
(EVA and EVB)
Interrupts
reset, etc.