Specifications

CAN Control Registers
10-20
Bits AAn are reset by writing a 1 from the CPU. Writing a 0 has no effect. If the
CPU tries to reset a bit and the CAN tries to set the bit at the same time, the
bit is set.
TRSn: Transmission Request Set (for mailbox n)
If TRSn is set, write access to the corresponding mailbox is denied, and the
message in mailbox n will be transmitted. Several TRS bits can be set simulta-
neously.
TRS bits can be set by the CPU (user) or the CAN module and reset by internal
logic. If the CPU tries to set a bit while the CAN tries to clear it, the bit is set.
TRS bits are set by the user writing a 1. Writing a 0 has no effect.
In the event of a remote frame request, the TRS bits are set by the CAN module
for mailboxes 2 and 3.
The TRSn bits are reset after a successful or an aborted transmission (if an
abort is requested).
A write to a mailbox with TRS set will have no effect and will generate the WDIF
interrupt if enabled. A successful transmission initiates a mailbox interrupt, if
enabled.
TRS bits are used for mailboxes 4 and 5, and also for 2 and 3 if they are config-
ured for transmission.
TRRn: Transmission Request Reset (for mailbox n)
TRR bits can only be set by the CPU (user) and reset by internal logic. In case
the CPU tries to set a bit while the CAN module tries to clear it, the bit is set.
The TRR bits are set by the user writing a 1. Writing a 0 has no effect.
If TRRn is set, write access to the corresponding mailbox n is denied. A write
access will initiate a WDIF interrupt, if enabled. If TRRn is set and the transmis-
sion which was initiated by TRSn is not currently processed, the correspond-
ing transmission request will be cancelled. If the corresponding message is
currently processed, this bit is reset in the event of:
1) A successful transmission
2) An abort due to a lost arbitration
3) An error condition detected on the CAN bus line
If the transmission is successful, the status bit TAn is set. If the transmission
is aborted, the corresponding status bit AAn is set. In case of an error condi-
tion, an error status bit is set in the ESR.