Specifications

CAN Control Registers
10-19 CAN Controller Module
Mailbox enable bits are defined as follows:
0 Disable mailbox
1 Enable mailbox
10.4.2 Transmit Control Register (TCR)
The transmit control register (TCR) contains bits that control the transmission
of messages (see Figure 10–12).
The control bits to set or reset a transmission request (TRS and TRR, respec-
tively) can be written independently. In this way, a write access to these regis-
ters does not set bits that were reset because of a completed transmission.
After power-up, all bits are cleared.
Figure 10–12. Transmission Control Register (TCR) — Address 7101h
15 14 13 12 11 10 9 8
TA5
TA4 TA3 TA2 AA5 AA4 AA3 AA2
RC-0 RC-0 RC-0 RC-0 RC-0 RC-0 RC-0 RC-0
76543210
TRS5
TRS4 TRS3 TRS2 TRR5 TRR4 TRR3 TRR2
RS-0 RS-0 RS-0 RS-0 RS-0 RS-0 RS-0 RS-0
Note: R = Read access; C = Clear; S = Set only; value following dash (–) = value after reset
TAn: Transmission Acknowledge (for mailbox n)
If the message in mailbox n was sent successfully, bit TAn is set.
Bits TAn are reset by writing a 1 from the CPU. This also clears the interrupt
if an interrupt was generated. Writing a 0 has no effect. If the CPU tries to reset
the bit while the CAN tries to set it, the bit is set.
These bits set a mailbox interrupt flag (MIFx) in the IF register. The MIFx bits
initiate a mailbox interrupt if enabled; that is, if the corresponding interrupt
mask bit in the IM register is set.
AAn: Abort Acknowledge (for mailbox n)
If transmission of the message in mailbox n is aborted, bit AAn is set and the
AAIF bit in the IF register is set. The AAIF bit generates an error interrupt if
enabled.