Specifications

Message Objects
10-13 CAN Controller Module
During accesses to the data field or control field, it is critical that the data does
not change while the CAN module is reading it. Therefore, a write access to
the data field or control field is disabled for a receive mailbox. For transmit mail-
boxes, the access is usually denied if the transmit request set (TRS) bit or the
transmit request reset (TRR) bit is set. In these cases, a write-denied interrupt
flag (WDIF) is asserted. A way to access mailboxes 2 and 3 is to set the change
data field request (CDR) bit before accessing the mailbox data.
After the CPU access is finished, the CPU must clear the CDR flag by writing
a 0 to it. The CAN module checks for that flag before and after reading the mail-
box. If the CDR flag is set during the mailbox checks, the CAN module does
not transmit the message but continues to look for other transmit requests. The
setting of the CDR flag also stops the write-denied interrupt (WDI) from being
asserted.
10.3.4 Transmit Mailbox
Mailboxes 4 and 5 are transmit mailboxes only; whereas, mailboxes 2 and 3
can be configured for reception or transmission.
The CPU stores the data to be transmitted in a mailbox that is configured as
a transmit mailbox. After writing the data and the identifier into RAM, and pro-
vided the corresponding TRS bit has been set, the message is sent.
If more than one mailbox is configured as a transmit mailbox and more than
one corresponding TRS bit is set, the messages are sent one after another,
in falling order, beginning with the highest enabled mailbox.
If a transmission fails due to a law of arbitration or an error, the message trans-
mission will be re-attempted.
10.3.5 Receive Mailbox
Mailboxes 0 and 1 are receive-only mailboxes. Mailboxes 2 and 3 can be con-
figured for reception or transmission.
The identifier of each incoming message is compared to the identifiers held in
the receive mailboxes by using the appropriate identifier mask. When equality
is detected, the received identifier, the control bits, and the data bytes are writ-
ten into the matching RAM location. At the same time, the corresponding re-
ceive message pending (RMPn) bit is set and a mailbox interrupt (MIFx) is gen-
erated if enabled. If the current identifier does not match, the message is not
stored. The RMPn bit has to be reset by the CPU after reading the data.
If a second message has been received for this mailbox and the RMP bit is
already set, the corresponding receive message lost (RML) bit is set. In this