Specifications

Overview of the CAN Network
10-8
The mailboxes are located in one 48 × 16 RAM with 16-bit access and can be
written to or read by the CPU (user) or CAN. The CAN write or read access,
as well as the CPU read access, needs one clock cycle. The CPU write access
needs two clock cycles because the CAN controller performs a read-modify-
write cycle; and therefore, inserts one wait state for the CPU.
Table 10–3 shows the mailbox locations in the RAM.
Table 10–3. Mailbox Addresses
Mailboxes
Registers
MBOX_0
MBOX_1 MBOX_2 MBOX_3 MBOX_4 MBOX_5
MSG_ID n L 7200 7208 7210 7218 7220 7228
MSG_ID n H 7201 7209 7211 7219 7221 7229
MSG_CTRL n 7202 720A 7212 721A 7222 722A
Reserved
MBOX n A 7204 720C 7214 721C 7224 722C
MBOX
n B 7205 720D 7215 721D 7225 722D
MBOX n C 7206 720E 7216 721E 7226 722E
MBOX
n D 7207 720F 7217 721F 7227 722F