Specifications

Overview of the CAN Network
10-7 CAN Controller Module
Table 10–2. Register Addresses
Address Name Description
7100h MDER Mailbox Direction/Enable Register (bits 7 to 0)
7101h TCR Transmission Control Register (bits 15 to 0)
7102h RCR Receive Control Register (bits 15 to 0)
7103h MCR Master Control Register (bits 13 to 6, 1, 0)
7104h BCR2 Bit Configuration Register 2 (bits 7 to 0)
7105h BCR1 Bit Configuration Register 1 (bits 10 to 0)
7106h ESR Error Status Register (bits 8 to 0)
7107h GSR Global Status Register (bits 5 to 0)
7108h CEC Transmit and Receive Error Counters (bits 15 to 0)
7109h CAN_IFR Interrupt Flag Register (bits 13 to 8, 6 to 0)
710Ah CAN_IMR Interrupt Mask Register (bits 15, 13 to 0)
710Bh LAM0_H Local Acceptance Mask for MBOX0 and 1 (bits 31, 28 to 16)
710Ch LAM0_L Local Acceptance Mask for MBOX0 and 1 (bits 15 to 0)
710Dh LAM1_H Local Acceptance Mask for MBOX2 and 3 (bits 31, 28 to 16)
710Eh LAM1_L Local Acceptance Mask for MBOX2 and 3 (bits 15 to 0)
710Fh
Reserved Accesses assert the CAADDRx signal from the CAN peripheral
(which will assert an Illegal Address error)
Note: All unimplemented register bits are read as zero; writes have no effect. All register bits are initialized to zero unless other-
wise stated in the definition.