Specifications

SPI Control Registers
9-28
9.5.9 SPI Priority Control Register (SPIPRI)
The SPIPRI selects the interrupt priority level of the SPI interrupt and controls
the SPI operation on the XDS emulator during program suspends, such as hit-
ting a breakpoint.
Figure 9–15. SPI Priority Control Register (SPIPRI) — Address 704Fh
7 6 5 4 3–0
Reserved
SPI_
PRIORITY
SPI_SUSP_
SOFT
SPI_SUSP_
FREE
Reserved
R-0 RW RW RW-0 R-0
Note: R = Read access, W = Write access, -0 = value after reset
Bit 7 Reserved. Reads return zero; writes have no effect.
Bit 6 SPI_PRIORITY. Interrupt Priority Select. This bit specifies the priority level of
the SPI interrupt.
0 Interrupts are high-priority requests.
1 Interrupts are low-priority requests.
Bits 5–4 SPI_SUSP_SOFT and FREE bits. These bits determine what occurs when
an emulation suspend occurs (for example, when the debugger hits a break-
point). The peripheral can continue whatever it is doing (free run mode) or, if in
stop mode, it can either stop immediately or stop when the current operation
(the current receive/transmit sequence) is complete.
Bit 5 Bit 4
Soft Free
0 0 Immediate stop on suspend.
1 0 Complete current receive/transmit sequence before
stopping.
X 1 Free run, continue SPI operation regardless of suspend.
Bits 3–0 Reserved. Reads return zero; writes have no effect.