Specifications

SPI Control Registers
9-27 Serial Peripheral Interface (SPI)
9.5.8 SPI Serial Data Register (SPIDAT)
The SPIDAT is the transmit/receive shift register. Data written to the SPIDAT
is shifted out (MSB) on subsequent SPICLK cycles. For every bit shifted out
(MSB) of the SPI, a bit is shifted into the LSB end of the shift register.
Figure 9–14. SPI Serial Data Register (SPIDAT) — Address 7049h
15 14 13 12 11 10 9 8
SDAT15
SDAT14 SDAT13 SDAT12 SDAT11 SDAT10 SDAT9 SDAT8
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
76543210
SDAT7
SDAT6 SDAT5 SDAT4 SDAT3 SDAT2 SDAT1 SDAT0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, -0 = value after reset
Bits 15–0 SDAT15–SDAT0. Serial Data. Writing to the SPIDAT performs two functions:
- It provides data to be output on the serial output pin if the TALK bit
(SPICTL.1) is set.
- When the SPI is operating as a master, a data transfer is initiated. When
initiating a transfer, see the CLOCK_POLARITY bit (SPICCR.6) and the
CLOCK_PHASE bit (SPICTL.3) for the requirements.
In master mode, writing dummy data to SPIDAT initiates a receiver sequence.
Since the data is not hardware-justified for characters shorter than sixteen bits,
transmit data must be written in left-justified form, and received data read in
right-justified form.