Specifications

SPI Control Registers

9-26

9.5.7 SPI Serial Transmit Buffer Register (SPITXBUF)

The SPITXBUF stores the next character to be transmitted. Writing to this reg-

ister sets the TX_BUF_FULL (SPISTS.5) flag. When transmission of the cur-

rent character is complete, the contents of this register are automatically

loaded in SPIDAT and the TX_BUF_FULL flag is cleared. If no transmission

is currently active, data written to this register falls through into the SPIDAT

In master mode, if no transmission is currently active, writing to this register

initiates a transmission in the same manner that writing to SPIDAT does.

Figure 9–13. SPI Serial Transmit Buffer Register (SPITXBUF) — Address 7048h

15 14 13 12 11 10 9 8

TXB15

TXB14 TXB13 TXB12 TXB11 TXB10 TXB9 TXB8

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

76543210

TXB7

TXB6 TXB5 TXB4 TXB3 TXB2 TXB1 TXB0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, -0 = value after reset

Bits 15–0 TXB15–TXB0. Transmit Data Buffer. This is where the next character to be

transmitted is stored. When the transmission of the current character has com-

pleted, if the TX_BUF_FULL flag is set, the contents of this register is automati-

cally transferred to SPIDAT, and the TX_BUF_FULL flag is cleared.

Note: Writes to SPITXBUF must be left-justified