Specifications

SPI Control Registers
9-24
9.5.5 SPI Emulation Buffer Register (SPIRXEMU)
The SPIRXEMU contains the received data. Reading the SPIRXEMU does not
clear the SPI INT FLAG bit (SPISTS.6). This is not a real register but a dummy
address from which the contents of SPIRXBUF can be read by the emulator
without clearing the SPI_INT_FLAG.
Figure 9–11.SPI Emulation Buffer Register (SPIRXEMU) — Address 7046h
15 14 13 12 11 10 9 8
ERXB15
ERXB14 ERXB13 ERXB12 ERXB11 ERXB10 ERXB9 ERXB8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
76543210
ERXB7
ERXB6 ERXB5 ERXB4 ERXB3 ERXB2 ERXB1 ERXB0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
Note: R = Read access, -0 = value after reset
Bits 15–0 ERXB15–ERXB0. Emulation Buffer Received Data. The SPIRXEMU func-
tions almost identically to the SPIRXBUF, except that reading the SPIRXEMU
does not clear the SPI INT FLAG bit (SPISTS.6). Once the SPIDAT has re-
ceived the complete character, the character is transferred to the SPIRXEMU
and SPIRXBUF, where it can be read. At the same time, SPI INT FLAG is set.
This mirror register was created to support emulation. Reading the SPIRXBUF
clears the SPI INT FLAG bit (SPISTS.6). In the normal operation of the emula-
tor, the control registers are read to continually update the contents of these
registers on the display screen. The SPIRXEMU was created so that the emu-
lator can read this register and properly update the contents on the display
screen. Reading SPIRXEMU does not clear the SPI INT FLAG, but reading
SPIRXBUF clears this flag. In other words, SPIRXEMU enables the emulator
to emulate the true operation of the SPI more accurately.
It is recommended that you view SPIRXEMU in the normal emulator run mode.