Specifications

SPI Control Registers
9-23 Serial Peripheral Interface (SPI)
9.5.4 SPI Baud Rate Register (SPIBRR)
The SPIBRR contains the bits used for baud-rate selection.
Figure 9–10. SPI Baud Rate Register (SPIBRR) — Address 7044h
76543210
Reserved
SPI BIT
RATE 6
SPI BIT
RATE 5
SPI BIT
RATE 4
SPI BIT
RATE 3
SPI BIT
RATE 2
SPI BIT
RATE 1
SPI BIT
RATE 0
R-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bit 7 Reserved. Reads return zero; writes have no effect.
Bits 6–0 SPI BIT RATE 6–SPI BIT RATE 0. SPI Bit Rate (Baud) Control. These bits de-
termine the bit transfer rate if the SPI is the network master. There are 125 data
transfer rates (each a function of the CPU clock, CLKOUT) that can be se-
lected. One data bit is shifted per SPICLK cycle. (SPICLK is the baud rate clock
output on the SPICLK pin.)
If the SPI is a network slave, the module receives a clock on the SPICLK pin
from the network master; therefore, these bits have no effect on the SPICLK
signal. The frequency of the input clock from the master should not exceed the
slave SPI’s SPICLK signal divided by 4.
In master mode, the SPI clock is generated by the SPI and is output on the
SPICLK pin. The SPI baud rates are determined by the formula in
Equation 9–2.
Equation 9–2. SPI Baud-Rate Calculations
- For SPIBRR = 3 to 127:
SPI Baud Rate
CLKOUT
(SPIBRR 1)
=
+
- For SPIBRR = 0, 1, or 2:
SPI Baud Rate
CLKOUT
4
=
where: CLKOUT = CPU clock frequency of the device
SPIBRR = Contents of the SPIBRR in the master SPI device