Specifications

SPI Control Registers
9-21 Serial Peripheral Interface (SPI)
impedance state. If this bit is disabled during a transmission, the transmit shift
register continues to operate until the previous character is shifted out. When
the TALK bit is disabled, the SPI is still able to receive characters and update
the status flags. TALK is cleared (disabled) by a system reset.
0 Disables transmission:
- Slave mode operation: If not previously configured as a general-
purpose I/O pin, the SPISOMI pin will be put in the high-
impedance state.
- Master mode operation: If not previously configured as a general-
purpose I/O pin, the SPISIMO pin will be put in the high-
impedance state.
1 Enables transmission
For the 4-pin option, ensure to enable the receiver’s SPISTB input
pin.
Bit 0 SPI_INT_ENA. SPI Interrupt Enable. This bit controls the SPI’s ability to gen-
erate a transmit/receive interrupt. The SPI INT FLAG bit (SPISTS.6) is unaf-
fected by this bit.
0 Disables interrupt
1 Enables interrupt
9.5.3 SPI Status Register (SPISTS)
The SPISTS register contains the receive buffer status bits.
Figure 9–9. SPI Status Register (SPISTS) — Address 7042h
7 6 5 4–0
RECEIVER_
OVERRUN_
FLAG
†‡
SPI_INT_FLAG
†‡
TX_BUF_FULL_
FLAG
‡
Reserved
RC-0 RC-0 RC-0 R-0
Note: R = Read access, C = Clear, -0 = value after reset
†
The RECEIVER_OVERRUN_FLAG bit and the SPI_INT_FLAG bit share the same interrupt vector.
‡
Writing a 0 to bits 5, 6, and 7 has no effect.
Bit 7 RECEIVER_OVERRUN_FLAG. SPI Receiver Overrun Flag. This bit is a read/
clear only flag. The SPI hardware sets this bit when a receive or transmit op-
eration completes before the previous character has been read from the buff-
er. The bit indicates that the last received character has been overwritten and
therefore lost (when the SPIRXBUF was overwritten by the SPI module before
the previous character was read by the user application). The SPI requests