Specifications

SPI Control Registers
9-20
9.5.2 SPI Operation Control Register (SPICTL)
The SPICTL operation control register controls data transmission, the SPI’s
ability to generate interrupts, the SPICLK phase, and the operational mode
(slave or master).
Figure 9–8. SPI Operation Control Register (SPICTL) — Address 7041h
7–5 43210
Reserved
OVERRUN_
INT_ENA
CLOCK_
PHASE
MASTER/
SLAVE
TALK
SPI_INT_
ENA
R-0 RW-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bits 7–5 Reserved. Reads return zero; writes have no effect.
Bit 4 OVERRUN_INT_ENA. Overrun Interrupt Enable. Setting this bit causes an in-
terrupt to be generated when the RECEIVER OVERRUN flag bit (SPISTS.7) is
set by hardware. Interrupts generated by the RECEIVER_OVERRUN flag bit
and the SPI_INT_FLAG bit (SPISTS.6) share the same interrupt vector.
0 Disable RECEIVER_OVERRUN flag bit (SPISTS.7) interrupts.
1 Enable RECEIVER_OVERRUN flag bit (SPISTS.7) interrupts.
Bit 3 CLOCK_PHASE. SPI Clock Phase Select. This bit controls the phase of the
SPICLK signal.
0 Normal SPI clocking scheme, depending on the CLOCK_POLAR-
ITY bit (SPICCR.6).
1 SPICLK signal delayed by one half-cycle; polarity determined by
the CLOCK_POLARITY bit.
CLOCK_PHASE and CLOCK_POLARITY (SPICCR.6) bits make four differ-
ent clocking schemes possible (see Figure 9–3). When operating with
CLOCK_PHASE high, the SPI (master or slave) makes the first bit of data
available after SPIDAT is written and before the first edge of the SPICLK sig-
nal, regardless of which SPI mode is being used.
Bit 2 MASTER/SLAVE. SPI Network Mode Control. This bit determines whether
the SPI is a network master or slave. During reset initialization, the SPI is auto-
matically configured as a network slave.
0 SPI configured as a slave.
1 SPI configured as a master.
Bit 1 TALK. Master/Slave Transmit Enable. The TALK bit can disable data trans-
mission (master or slave) by placing the serial data output in the high-