Specifications

SPI Control Registers
9-19 Serial Peripheral Interface (SPI)
1 Data is output on falling edge and input on rising edge. When no
SPI data is used, SPICLK is at high level.
The data input and output edges depend on the value of the
CLOCK_PHASE bit (SPICTL.3) as follows:
- CLOCK_PHASE = 0: Data is output on the falling edge of the
SPICLK signal; input data is latched on the rising edge of the
SPICLK signal.
- CLOCK_PHASE = 1: Data is output one half-cycle before the first
falling edge of the SPICLK signal and on subsequent rising
edges of the SPICLK signal; input data is latched on the falling
edge of the SPICLK signal.
Bits 5–4 Reserved. Reads return zero; writes have no effect.
Bits 3–0 SPI CHAR3–SPI CHAR0. Character Length Control Bits 3–0. These four bits
determine the number of bits to be shifted in or out as a single character during
one shift sequence.
Table 9–3 lists the character length selected by the bit values.
Table 9–3. Character Length Control Bit Values
SPI
CHAR3
SPI
CHAR2
SPI
CHAR1
SPI
CHAR0
Character Length
0 0 0 0 1
0001 2
0010 3
0011 4
0100 5
0101 6
0110 7
0111 8
1000 9
1001 10
1010 11
1011 12
1100 13
1101 14
1110 15
1
1 1 1 16