Specifications

SPI Control Registers
9-18
9.5.1 SPI Configuration Control Register (SPICCR)
The SPI Configuration Control Register (SPICCR) controls the setup of the
SPI for operation.
Figure 9–7. SPI Configuration Control Register (SPICCR) — Address 7040h
76 5–4 3210
SPI_SW_
RESET
CLOCK_
POLARITY
Reserved SPICHAR3 SPICHAR2 SPICHAR1 SPICHAR0
RW-0 RW-0 R-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bit 7 SPI_SW_RESET. SPI Software Reset. When changing configuration, you
should clear this bit before the changes and set this bit before resuming opera-
tion. (See Section 9.4.10 on page 9-15.)
0 Initializes the SPI operating flags to the reset condition.
Specifically, the RECEIVER_OVERRUN flag bit (SPISTS.7), the
SPI_INT_FLAG bit (SPISTS.6), and the TXBUF_FULL flag
(SPISTS.5) are cleared. The SPI configuration remains un-
changed. If the module is operating as a master, the SPICLK sig-
nal output returns to its inactive level.
1 SPI is ready to transmit or receive the next character.
When the SPI SW RESET bit is a 1, a character written to the
transmitter will not be shifted out when this bit clears. A new char-
acter must be written to the serial data register.
Bit 6 CLOCK_POLARITY. Shift Clock Polarity. This bit controls the polarity of the
SPICLK signal. CLOCK_POLARITY and CLOCK_PHASE (SPICTL.3) control
four clocking schemes on the SPICLK pin. See Section 9.4.8, SPI Clocking
Schemes , on page 9-12.
0 Data is output on rising edge and input on falling edge. When no
SPI data is sent, SPICLK is at low level.
The data input and output edges depend on the value of the
CLOCK_PHASE (SPICTL.3) bit as follows:
- CLOCK_PHASE = 0: Data is output on the rising edge of the
SPICLK signal; input data is latched on the falling edge of the
SPICLK signal.
- CLOCK_PHASE = 1: Data is output one half-cycle before the first
rising edge of the SPICLK signal and on subsequent falling edges
of the SPICLK signal; input data is latched on the rising edge of
the SPICLK signal.