Specifications

SPI Interrupts
9-16
Figure 9–5. Five Bits per Character
AC DEFG H I J
76 543 76 345
76 543 76 345
Master SPI
Int flag
Slave SPI
Int flag
SPISOMI
from slave
CLOCK POLARITY = 0
CLOCK PHASE = 0
CLOCK POLARITY = 1
CLOCK PHASE = 0
SPISIMO
from master
CLOCK POLARITY = 1
CLOCK PHASE = 1
CLOCK POLARITY = 0
CLOCK PHASE = 1
B
SPISTE
K
SPICLK signal options:
A. Slave writes 0D0h to SPIDAT and waits for the master to shift out the data.
B. Master sets the slave SPISTE signal low (active).
C. Master writes 058h to SPIDAT, which starts the transmission procedure.
D. First byte is finished and sets the interrupt flags.
E. Slave reads 0Bh from its SPIRXBUF (right justified).
F Slave writes 04Ch to SPIDAT and waits for the master to shift out the data.
G. Master writes 06Ch to SPIDAT, which starts the transmission procedure.
H. Master reads 01Ah from the SPIRXBUF (right justified).
I. Second byte is finished and sets the interrupt flags.
J. Master reads 89h and the slave reads 8Dh from their respective SPIRXBUF. After the user’s software masks off the
unused bits, the master receives 09h and the slave receives 0Dh.
K. Master clears the slave SPISTE signal high (inactive).