Specifications

SPI Interrupts
9-14
For the SPI, the SPICLK symmetry is retained only when the result of (SPIBRR
+ 1) is an even value. When (SPIBRR + 1) is an odd value and SPIBRR is
greater than 3, the SPICLK becomes asymmetrical. The low pulse of the
SPICLK is one CLKOUT longer than the high pulse when the CLOCK_PO-
LARITY bit is clear (0). When the CLOCK_POLARITY bit is set to 1, the high
pulse of the SPICLK is one CLKOUT longer than the low pulse, as shown in
Figure 9–4.
Figure 9–4. SPI: SPICLK-CLKOUT Characteristic when (BRR + 1) is Odd, BRR > 3, and
CLOCK POLARITY = 1
CLKOUT
SPICLK
2 cycles 3 cycles 2 cycles
9.4.9 Initialization Upon Reset
A system reset forces the SPI peripheral module into the following default con-
figuration:
- The unit is configured as a slave module (MASTER/SLAVE = 0).
- The transmit capability is disabled (TALK = 0).
- Data is latched at the input on the falling edge of the SPICLK signal.
- Character length is assumed to be one bit.
- The SPI interrupts are disabled.
- Data in SPIDAT is reset to 0000h.
- SPI module pin functions are selected as general-purpose inputs (this is
done in I/O Mux control regsiter B [MCRB]).
To change this SPI configuration:
1) Clear the SPI_SW_RESET bit (SPICCR.7) to 0 to force the SPI to the reset
state.
2) Initialize the SPI configuration, format, baud rate, and pin functions as de-
sired.
3) Set the SPI_SW_RESET bit to 1 to release the SPI from the reset state.
4) Write to SPIDAT or SPITXBUF (this initiates the communication process
in the master).
5) Read SPIRXBUF after the data transmission has completed
(SPISTS.6 = 1) to determine what data was received.