Specifications

SPI Interrupts
9-13 Serial Peripheral Interface (SPI)
- Rising Edge With Delay. The SPI transmits data one half-cycle ahead of
the rising edge of the SPICLK signal and receives data on the rising edge
of the SPICLK signal.
The selection procedure for the SPI clocking scheme is shown in Table 9–2.
Examples of these four clocking schemes relative to transmitted and received
data are shown in Figure 9–3.
Table 9–2. SPI Clocking Scheme Selection Guide
SPICLK Scheme
CLOCK POLARITY
(SPICCR.6)
CLOCK PHASE
(SPICTL.3)
Rising edge without delay 0 0
Rising edge with delay 0 1
Falling edge without delay 1 0
Falling edge with delay
1 1
Figure 9–3. SPICLK Signal Options
SPICLK cycle
number
12345678
SPICLK
(Falling edge
without delay)
SPICLK
(Falling edge
with delay)
SPISIMO/
SPISOMI
SPISTE
MSB LSB
Note: Previous data bit
(Into slave)
Receive latch
points
SPICLK
(Rising edge
without delay)
SPICLK
(Rising edge
with delay
)
See note