Specifications

SPI Interrupts
9-12
- For SPIBRR = 0, 1, or 2:
SPI Baud Rate
CLKOUT
4
=
where:
CLKOUT = CPU clock frequency of the device
SPIBRR = Contents of the SPIBRR in the master SPI device
To determine what value to load into SPIBRR, you must know the device sys-
tem clock (CLKOUT) frequency (which is device-specific) and the baud rate
at which you will be operating.
Example 9–2 shows how to determine the maximum baud rate at which a
’C24x can communicate. Assume that CLKOUT = 30 MHz.
Example 9–2. Maximum Baud-Rate Calculation
SPI Baud Rate
CLKOUT
(SPIBRR 1)
30 10
6
(3 1)
7.5 10
6
bps
=
+
=
+
=
×
×
The maximum master baud rate would be 5.0 Mbps.
9.4.8 SPI Clocking Schemes
The CLOCK_POLARITY (SPICCR.6) and CLOCK_PHASE (SPICTL.3) bits
control four different clocking schemes on the SPICLK pin. The CLOCK PO-
LARITY bit selects the active edge of the clock, either rising or falling. The
CLOCK_PHASE bit selects a half-cycle delay of the clock. The four different
clocking schemes are as follows:
- Falling Edge Without Delay. The SPI transmits data on the falling edge of
the SPICLK and receives data on the rising edge of the SPICLK.
- Falling Edge With Delay. The SPI transmits data one half-cycle ahead of
the falling edge of the SPICLK signal and receive data on the falling edge
of the SPICLK signal.
- Rising Edge Without Delay. The SPI transmits data on the rising edge of
the SPICLK signal and receive data on the falling edge of the SPICLK sig-
nal.