Specifications

SPI Interrupts
9-10
9.4.3 OVERRUN_INT_ENA Bit (SPICTL.4)
Setting the overrun interrupt enable bit allows the assertion of an interrupt
whenever the RECEIVER_OVERRUN flag bit (SPISTS.7) is set by hardware.
Interrupts generated by SPISTS.7 and by the SPI_INT_FLAG (SPISTS.6) bit
share the same interrupt vector.
0 Disable RECEIVER_OVERRUN flag bit interrupts.
1 Enable RECEIVER_OVERRUN flag bit interrupts.
9.4.4 RECEIVER_OVERRUN_FLAG Bit (SPISTS.7)
The RECEIVER_OVERRUN flag bit is set whenever a new character is re-
ceived and loaded into the SPIRXBUF before the previously received charac-
ter has been read from the SPIRXBUF. The RECEIVER_OVERRUN flag bit
must be cleared by software.
9.4.5 SPI PRIORITY Bit (SPIPRI.6)
The value of the SPI_PRIORITY bit determines the priority of the interrupt re-
quest from the SPI.
0 Interrupts are high-priority requests.
1 Interrupts are low-priority requests.
9.4.6 Data Format
Four bits (SPICCR.3–0) specify the number of bits (1 to 16) in the data charac-
ter. This information directs the state control logic to count the number of bits
received or transmitted to determine when a complete character has been pro-
cessed. The following statements apply to characters with fewer than 16 bits:
- Data must be left justified when written to SPIDAT and SPITXBUF.
- Data read back from SPIRXBUF is right justified.
- SPIRXBUF contains the most recently received character, right justified,
plus any bits that remain from previous transmission(s) that have been
shifted to the left (shown in Example 9–1).