Specifications

SPI Operation
9-7 Serial Peripheral Interface (SPI)
Figure 9–2. SPI Master/Slave Connection
SPI master (master/slave = 1) SPI slave (master/slave = 0)
SPIRXBUF.15–0
Serial input buffer
SPIRXBUF
Shift register
(SPIDAT)
SPITXBUF.15–0
Serial transmit buffer
SPITXBUF
Processor 1
SPIDAT.15–0
SPICLK
SPISOMI
SPISTE
SPISIMO
SPICLK
SPISOMI
SPISTE
SPISIMO
Slave in/
master out
SPI
strobe
Slave out/
master in
Serial
clock
SPIRXBUF.15–0
Serial input buffer
SPIRXBUF
Shift register
(SPIDAT)
SPITXBUF.15–0
Serial transmit buffer
SPITXBUF
SPIDAT.15–0
Processor 2
LSBMSB LSBMSB
9.3.2 SPI Module Slave and Master Operation Modes
The SPI can operate in master or slave mode. The MASTER/SLAVE bit
(SPICTL.2) selects the operating mode and the source of the SPICLK signal.
Master Mode
In the master mode (MASTER/SLAVE = 1), the SPI provides the serial clock
on the SPICLK pin for the entire serial communications network. Data is output
on the SPISIMO pin and latched from the SPISOMI pin.
The SPIBRR determines both the transmit and receive bit transfer rate for the
network. The SPIBRR can select 126 different data transfer rates
Data written to SPIDAT or SPITXBUF initiates data transmission on the SPISI-
MO pin, MSB (most significant bit) first. Simultaneously, received data is
shifted through the SPISOMI pin into the LSB (least significant bit) of SPIDAT.
When the selected number of bits has been transmitted, the received data is
transferred to the SPIRXBUF (buffered receiver) for the CPU to read. Data is
stored right-justified in SPIRXBUF.
When the specified number of data bits has been shifted through SPIDAT, the
following events occur:
- SPIDAT contents are transferred to SPIRXBUF.
- SPI INT FLAG bit (SPISTS.6) is set to 1.