Specifications

SPI Control Registers
9-4
9.2 SPI Control Registers
Nine registers inside the SPI module (listed in Table 9–1) control the SPI op-
erations:
- SPICCR (SPI configuration control register). Contains control bits used for
SPI configuration
J SPI module software reset
J SPICLK polarity selection
J Four SPI character-length control bits
- SPICTL (SPI operation control register). Contains control bits for data
transmission
J Two SPI interrupt enable bits
J SPICLK phase selection
J Operational mode (master/slave)
J Data transmission enable
- SPISTS (SPI status register). Contains two receiver buffer status bits
J RECEIVER OVERRUN
J SPI INT FLAG
- SPIBRR (SPI baud rate register). Contains seven bits that determine the
bit transfer rate
- SPIRXEMU (SPI receive emulation buffer register). Contains the received
data. This register is used for emulation purposes only. The SPIRXBUF
should be used for normal operation
- SPIRXBUF (SPI receive buffer — the serial receive buffer register). Con-
tains the received data
- SPITXBUF (SPI transmit buffer — the serial transmit buffer register). Con-
tains the next character to be transmitted
- SPIDAT (SPI data register). Contains data to be transmitted by the SPI,
acting as the transmit/receive shift register. Data written to SPIDAT is
shifted out on subsequent SPICLK cycles. For every bit shifted out of the
SPI, a bit from the receive bit stream is shifted into the other end of the shift
register
- SPIPRI (SPI priority register). Contains bits that specify interrupt priority
and determine SPI operation on the XDS emulator during program sus-
pensions