Specifications

Differences vs. ’C240 SPI
9-2
9.1 Differences vs. ’C240 SPI
This SPI has 16-bit transmit and receive capability, with double-buffered trans-
mit and double-buffered receive. All data registers are 16-bits wide.
The SPI is no longer limited to a maximum transmission rate of CLKOUT / 8
in slave mode. The maximum transmission rate in both slave mode and master
mode is now CLKOUT / 4.
Note that there is a software change required since writes of transmit data to
the serial data register, SPIDAT (and the new transmit buffer, SPITXBUF),
must be left-justified. On the ’C240, these writes had to be left-justified within
an 8-bit register. Now they must be left justified within a 16-bit register.
The control and data bits for general-purpose bit I/O multiplexing have been
removed from this peripheral, along with the associated registers, SPIPC1
(704Dh) and SPIPC2 (704Eh). These bits are now in the General-Purpose I/O
registers.
The polarity of the SPI_SW_RESET bit in ’240x is the opposite of the ’240 SPI.
9.1.1 SPI Physical Description
The SPI module, as shown in Figure 9–1, consists of:
- Four I/O pins:
J SPISIMO (SPI slave in, master out)
J SPISOMI (SPI slave out, master in)
J SPICLK (SPI clock)
J SPISTE (SPI slave transmit enable)
- Master and slave mode operations
- SPI serial receive buffer register (SPIRXBUF)
This buffer register contains the data that is received from the network and
that is ready for the CPU to read
- SPI serial transmit buffer register (SPITXBUF)
This buffer register contains the next character to be transmitted when the
current transmit has completed
- SPI serial data register (SPIDAT).
This data shift register serves as the transmit/receive shift register
- SPICLK phase and polarity control