Specifications

SCI Module Registers
8-31 Serial Communications Interface (SCI)
8.6.8 Priority Control Register
The Priority Control Register contains the receiver and transmitter interrupt
priority select bits and controls the SCT operation on the XDS emulator during
program suspends such as hitting a breakpoint.
Figure 8–20. SCI Priority Control Register (SCIPRI) — Address 705Fh
76543 2–0
Reserved
SCITX
PRIORITY
SCIRX
PRIORITY
SCI SOFT SCI FREE Reserved
R-0 RW-0 RW-0 RW-0 RW-0 R-0
Note: R = Read access, W = Write access, -0 = value after reset
Bit 7 Reserved. Reads return zero; writes have no effect.
Bit 6 SCITX PRIORITY. SCI transmitter interrupt priority select. This bit specifies
priority level of the SCI transmitter interrupts.
0 Interrupts are high-priority requests.
1 Interrupts are low-priority requests.
Bit 5 SCIRX PRIORITY. SCI receiver interrupt priority select. This bit specifies the
priority level to the SCI receiver interrupts.
0 Interrupts are high-priority requests.
1 Interrupts are low-priority requests.
Bits 4,3 SCI SUSP SOFT & FREE bits. These bits determine what occurs when an
emulation suspend occurs (for example, when the debugger hits a break-
point). The peripheral can continue whatever it is doing (free-run mode), or if in
stop mode, it can either stop immediately or stop when the current operation
(the current receive/transmit sequence) is complete.
Bit 4 Bit 3
Soft Free
0 0 Immediate stop on suspend.
1 0 Complete current receive/transmit sequence before
stopping.
X 1 Free run, continue SCI operation regardless of suspend.
Bits 2–0 Reserved. Reads return zero; writes have no effect.