Specifications

SCI Module Registers
8-30
SCIRXEMU is not physically implemented, it is just a different address location
to access the SCIRXBUF register without clearing the RXRDY flag.
Figure 8–17. Emulation Data Buffer Register (SCIRXEMU) — Address 7056h
76543210
ERXDT7
ERXDT6 ERXDT5 ERXDT4 ERXDT3 ERXDT2 ERXDT1 ERXDT0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
Note: R = Read access, -0 = value after reset
8.6.6.2 Receiver Data Buffer
When the current data received is shifted from RXSHF to the receive buffer,
flag bit RXRDY is set and the data is ready to be read. If the RX/BK INT ENA
bit (SCICTL2.1) is set, this shift also causes an interrupt. When SCIRXBUF is
read, the RXRDY flag is reset. SCIRXBUF is cleared by a system reset.
Figure 8–18. Receiver Data Buffer (SCIRXBUF) — Address 7057h
76543210
RXDT7
RXDT6 RXDT5 RXDT4 RXDT3 RXDT2 RXDT1 RXDT0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
Note: R = Read access, -0 = value after reset
8.6.7 Transmit Data Buffer Register
Data bits to be transmitted are written to the transmit data buffer (SCITXBUF)
register. The transfer of data from this register to the TXSHF transmitter shift
register sets the TXRDY flag (SCICTL2.7), indicating that SCITXBUF is ready
to receive another set of data. If bit TX INT ENA (SCICTL2.0) is set, this data
transfer also causes an interrupt. These bits must be right-justified because
the leftmost bits are ignored for characters less than eight bits long.
Figure 8–19. Transmit Data Buffer Register (SCITXBUF) — Address 7059h
76543210
TXDT7
TXDT6 TXDT5 TXDT4 TXDT3 TXDT2 TXDT1 TXDT0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset