Specifications

SCI Module Registers
8-28
causes a receiver interrupt to be generated if the RX/BK INT ENA bit is a 1,
but it does not cause the receiver buffer to be loaded. A BRKDT interrupt can
occur, even if the receiver SLEEP bit is set to 1. BRKDT is cleared by an active
SW RESET or by a system reset. It is not cleared by receipt of a character after
the break is detected. In order to receive more characters, the SCI must be
reset by toggling the SW RESET bit or by a system reset.
0 No break condition.
1 Break condition occurred.
Bit 4 FE. SCI framing-error flag.
The SCI sets this bit when an expected stop bit is not found. Only the first stop
bit is checked. The missing stop bit indicates that synchronization with the start
bit has been lost and that the character is incorrectly framed. It is reset by clear-
ing the SW RESET bit or by a system reset.
0 No framing error detected.
1 Framing error detected.
Bit 3 OE. SCI overrun-error flag.
The SCI sets this bit when a character is transferred into registers SCIRXEMU
and SCIRXBUF before the previous character is fully read by the CPU or
DMAC. The previous character is overwritten and lost. The OE flag is reset by
an active SW RESET or by a system reset.
0 No overrun error detected.
1 Overrun error detected.
Bit 2 PE. SCI parity-error flag.
This flag bit is set when a character is received with a mismatch between the
number of 1s and its parity bit. The address bit is included in the calculation.
If parity generation and detection is not enabled, the PE flag is disabled and
read as 0. The PE bit is reset by an active SW RESET or a system reset.
0 No parity error or parity is disabled.
1 Parity error is detected.