Specifications

SCI Module Registers

8-27

Serial Communications Interface (SCI)

8.6.5 Receiver Status Register

The receiver status (SCIRXST) register contains seven bits that are receiver

status flags (two of which can generate interrupt requests). Each time a com-

plete character is transferred to the receive buffers (SCIRXEMU and SCIRX-

BUF), the status flags are updated. Each time the buffers are read, the flags

are cleared. Figure 8–16 on page 8-29 shows the relationships between sev-

eral of the register’s bits.

Figure 8–15. Receiver Status Register (SCIRXST) — Address 7055h

76543210

ERROR

RXRDY BRKDT FE OE PE RXWAKE Reserved

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

Note: R = Read access, W = Write access, -0 = value after reset

Bit 7 RX ERROR. SCI receiver-error flag.

The RX ERROR flag indicates that one of the error flags in the receiver status

overrun, and parity error enable flags (bits 5–2: BRKDT, FE, OE, and PE).

0 No error flags set.

1 Error flag(s) set.

A 1 on this bit will cause an interrupt if the RX ERR INT ENA bit (SCICTL1.6)

is set. This bit can be used for fast error-condition checking during the interrupt

service routine. This error flag cannot be cleared directly; it is cleared by an

active SW RESET or by a system reset.

Bit 6 RXRDY. SCI receiver-ready flag.

When a new character is ready to be read into the SCIRXBUF register, the re-

ceiver sets this bit, and a receiver interrupt is generated if the RX/BK INT ENA

bit (SCICTL2.1) is a 1. RXRDY is cleared by reading the SCIRXBUF register,

by an active SW RESET, or by a system reset.

0 No new character in SCIRXBUF.

1 Character ready to be read from SCIRXBUF.

Bit 5 BRKDT. SCI break-detect flag.

The SCI sets this bit when a break condition occurs. A break condition occurs

when the SCI receive data line (SCIRXD) remains continuously low for at least

ten bits, beginning after a missing first stop bit. The occurrence of a break