Specifications

SCI Module Registers
8-26
8.6.4 SCI Control Register 2
SCI control register 2 enables the receive-ready, break-detect, and transmit-
ready interrupts as well as transmitter-ready and -empty flags.
Figure 8–14. SCI Control Register 2 (SCICTL2) — Address 7054h
7 6 5–2 1 0
TXRDY
TX EMPTY Reserved RX/BK INT ENA TX INT ENA
R-1 R-1 R-0 RW-0 RW-0
Note: R = Read access, W = Write access, -n = value after reset
Bit 7 TXRDY. Transmitter buffer-register ready flag.
When set, this bit indicates that the transmit buffer register, SCITXBUF, is
ready to receive another character. Writing data to the SCITXBUF automati-
cally clears this bit. When set, this flag asserts a transmitter interrupt request
if the interrupt-enable bit TX INT ENA (SCICTL2.0) is also set. TXRDY is set
to 1 by enabling the SW RESET bit (SCICTL.2) or by a system reset.
0 SCITXBUF is full.
1 SCITXBUF is ready to receive the next character.
Bit 6 TX EMPTY. Transmitter empty flag.
This flag’s value indicates the contents of the transmitter’s buffer register
(SCITXBUF) and shift register (TXSHF). An active SW RESET (SCICTL1.2),
or a system reset, sets this bit. This bit
does not cause an interrupt request.
0 Transmitter buffer or shift register or both are loaded with data.
1 Transmitter buffer and shift registers are both empty.
Bits 5–2 Reserved.
Reads return zero; writes have no effect.
Bit 1 RX/BK INT ENA. Receiver-buffer/break interrupt enable.
This bit controls the interrupt request caused by
either the RXRDY flag or the
BRKDT flag (bits SCIRXST.6 and .5) being set. However, RX/BRK INT ENA
does not prevent the setting of these flags.
0 Disable RXRDY/BRKDT interrupt.
1 Enable RXRDY/BRKDT interrupt.
Bit 0 TX INT ENA. SCITXBUF-register interrupt enable.
This bit controls issuing an interrupt request caused by setting the TXRDY flag
bit (SCICTL2.7). However, it doesn’t prevent the TXRDY flag from being set
(being set indicates that register SCITXBUF is ready to receive another char-
acter).
0 Disable TXRDY interrupt.
1 Enable TXRDY interrupt.