Specifications

SCI Module Registers
8-24
tus bits (SCIRXST.5–2: BRKDT, FE, OE, and PE) unless the address byte is
detected. This bit is not cleared when the address byte is detected.
Bit 1 TXENA. SCI transmitter enable.
Data is transmitted through the SCITXD pin only when TXENA is set. If reset,
transmission is halted but only after all data previously written to SCITXBUF
has been sent.
0 Transmitter disabled
1 Transmitter enabled
Bit 0 RXENA. SCI receiver enable.
Data is received on the SCIRXD pin and is sent to the receive shift register and
then the receive buffers. This bit enables or disables the receiver (transfer to
the buffers).
0 Prevent received characters from transfer into the SCIRXEMU and
SCIRXBUF receive buffers.
1 Send receive characters into the SCIRXEMU and SCIRXBUF
buffers.
Clearing RXENA stops received characters from being transferred into the two
receive buffers and also stops the generation of receiver interrupts. However,
the receiver shift register can continue to assemble characters. Thus, if RXE-
NA is set during the reception of a character, the complete character will be
transferred into the receive buffer registers, SCIRXEMU and SCIRXBUF.