Specifications

SCI Module Registers
8-23 Serial Communications Interface (SCI)
Table 8–5. SW RESET-Affected Flags
SCI Flag Register.Bit Value After SW RESET
TXRDY SCICTL2.7 1
TX EMPTY SCICTL2.6 1
RXWAKE SCIRXST.1 0
PE SCIRXST.2 0
OE SCIRXST.3 0
FE SCIRXST.4 0
BRKDT SCIRXST.5 0
RXRDY SCIRXST.6 0
RX ERROR
SCIRXST.7 0
Once SW RESET is asserted, the flags are frozen until the bit is de-asserted.
Bit 4 Reserved. Reads return zero; writes have no effect.
Bit 3 TXWAKE. SCI transmitter wakeup method select.
The TXWAKE bit controls selection of the data-transmit feature, depending on
which transmit mode (idle line or address bit) is specified at the ADDR/IDLE
MODE bit (SCICCR.3)
0 Transmit feature is not selected.
1 Transmit feature selected is dependent on the mode: idle-line or
address-bit:
In
idle-line mode: write a 1 to TXWAKE, then write data to register
SCITXBUF to generate an idle period of 11 data bits.
In
address-bit mode: write a 1 to TXWAKE, then write data to
SCITXBUF to set the address bit for that frame to 1.
TXWAKE is not cleared by the SW RESET bit (SCICTL1.5); it is cleared by a
system reset or the transfer of TXWAKE to the WUT flag.
Bit 2 SLEEP. SCI sleep.
In a multiprocessor configuration, this bit controls the receive sleep function.
Clearing this bit brings the SCI out of the sleep mode.
0 Sleep mode disabled
1 Sleep mode enabled
The receiver still operates when the SLEEP bit is set; however, operation does
not update the receive buffer ready bit (SCIRXST.6, RXRDY) or the error sta-