Specifications

SCI Module Registers

8-22

8.6.2 SCI Control Register 1

The SCI control register 1 controls the receiver/transmitter enable, TXWAKE

and SLEEP functions, and the SCI software reset.

Figure 8–11.SCI Control Register 1 (SCICTL1) — Address 7051h

76543210

Reserved

RX ERR

INT ENA

RESET

Reserved TXWAKE SLEEP TXENA RXENA

R-0 RW-0 RW-0 R-0 RS-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, S = Set only, -0 = value after reset

Bit 7 Reserved. Reads return zero; writes have no effect.

Bit 6 RX ERR INT ENA. SCI receiver enable.

Setting this bit enables an interrupt if the RX ERROR bit (SCIRXST.7) be-

comes set because of errors occurring.

0 Receive error interrupt disabled

1 Receive error interrupt enabled

Bit 5 SW RESET. SCI software reset (active low).

Writing a 0 to this bit initializes the SCI state machines and operating flags (reg-

isters SCICTL2 and SCIRXST) to the reset condition.

The SW RESET bit does not affect any of the configuration bits.

All affected logic is held in the specified reset state until a 1 is written to SW

RESET (the bit values following a reset are shown beneath each register dia-

gram in this section). Thus, after a system reset, re-enable the SCI by writing

a 1 to this bit.

Clear this bit after a receiver break detect (BRKDT flag, bit SCIRXST.5).

SW RESET affects the operating flags of the SCI, but it neither affects the con-

figuration bits nor restores the reset values. Table 8–5 lists the affected flags.