Specifications

SCI Module Registers
8-20
8.6.1 SCI Communication Control Register
The SCI communication control (SCICCR) register defines the character for-
mat, protocol, and communications mode used by the SCI.
Figure 8–10. SCI Communication Control Register (SCICCR) — Address 7050h
76543210
STOP
BITS
EVEN/ODD
PARITY
PARITY
ENABLE
LOOPBACK
ENA
ADDR/IDLE
MODE
SCICHAR2 SCICHAR1 SCICHAR0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bit 7 STOP BITS. SCI number of stop bits.
This bit specifies the number of stop bits transmitted. The receiver checks for
only one stop bit.
0 One stop bit
1 Two stop bits
Bit 6 PARITY. SCI parity odd/even selection.
If the PARITY ENABLE bit (SCICCR.5) is set, PARITY (bit 6) designates odd
or even parity (odd or even number of bits with the value of 1 in both transmitted
and received characters).
0 Odd parity
1 Even parity
Bit 5 PARITY ENABLE. SCI parity enable.
This bit enables or disables the parity function. If the SCI is in the address-bit
multiprocessor mode (set using bit 3 of this register), the address bit is included
in the parity calculation (if parity is enabled). For characters of less than eight
bits, the remaining unused bits should be masked out of the parity calculation.
0 Parity disabled; no parity bit is generated during transmission or is
expected during reception
1 Parity is enabled
Bit 4 LOOP BACK ENA. Loop Back test mode enable.
This bit enables the Loop Back test mode where the Tx pin is internally con-
nected to the Rx pin.
0 Loop Back test mode disabled
1 Loop Back test mode enabled