Specifications

SCI Port Interrupts
8-17 Serial Communications Interface (SCI)
8.5 SCI Port Interrupts
The internally-generated serial clock is determined by the device clock fre-
quency and the baud-select registers. The SCI uses the 16-bit value of the
baud-select registers to select one of 64k different serial clock rates.
The SCI’s receiver and transmitter can be interrupt controlled. The SCICTL2
register has one flag bit (TXRDY) that indicates active interrupt conditions, and
the SCIRXST register has two interrupt flag bits (RXRDY and BRKDT), plus
the RX ERROR interrupt flag which is a logical OR of the FE, OE & PE condi-
tions. The transmitter and receiver have separate interrupt-enable bits. When
not enabled, the interrupts are not asserted; however, the condition flags re-
main active, reflecting transmission and receipt status.
The SCI has independent peripheral interrupt vectors for the receiver and
transmitter. Peripheral interrupt requests can be either high priority or low
priority. This is indicated by the priority bits which are output from the peripheral
to the PIE controller. SCI interrupts can be programmed to assert the high- or
low-priority levels by the SCIRX PRIORITY (SCIPRI.5) and SCITX PRIORITY
(SCIPRI.6) control bits. When both RX and TX interrupt requests are made at
the same priority level, the receiver always has higher priority than the trans-
mitter, reducing the possibility of receiver overrun.
The operation of peripheral interrupts is described in the Peripheral Interrupt
Expansion controller chapter of the device specification of which this SCI
chapter is a part.
- If the RX/BK INT ENA bit (SCICTL2.1) is set, the receiver peripheral inter-
rupt request is asserted when one of the following events occurs:
J The SCI receives a complete frame and transfers the data in the
RXSHF register to the SCIRXBUF register. This action sets the
RXRDY flag (SCIRXST.6) and initiates an interrupt.
J A break detect condition occurs (the SCIRXD is low for ten bit periods
following a missing stop bit). This action sets the BRKDT flag bit
(SCIRXST.5) and initiates an interrupt.
- If the TX INT ENA bit (SCICTL2.0) is set, the transmitter peripheral inter-
rupt request is asserted whenever the data in the SCITXBUF register is
transferred to the TXSHF register, indicating that the CPU can write to the
TXBUF; this action sets the TXRDY flag bit (SCICTL2.7) and initiates an
interrupt.
Note:
Interrupt generation due to RXRDY and BRKDT bits are controlled by RX/
BK_INT_ENA bit (SCICTL2.1). Interrupt generation due to RX_ERROR bit
is controlled by RX_ERR_INT_ENA bit (SCICTL1.6).