Specifications

SCI Communication Format
8-14
8.4 SCI Communication Format
The SCI asynchronous communication format uses either single line (one
way) or two line (two way) communications. In this mode, the frame consists
of a start bit, one to eight data bits, an optional even/odd parity bit, and one or
two stop bits (shown in Figure 8–6). There are
eight SCICLK periods per data
bit.
The receiver begins operation on receipt of a valid start bit. A valid start bit is
identified by four consecutive internal SCICLK periods of zero bits as shown
in Figure 8–6. If any bit is not zero, then the processor starts over and begins
looking for another start bit.
For the bits following the start bit, the processor determines the bit value by
making three samples in the middle of the bits. These samples occur on the
fourth, fifth, and sixth SCICLK periods, and bit-value determination is on a ma-
jority (two out of three) basis. Figure 8–6 illustrates the asynchronous commu-
nication format for this with a start bit showing how edges are found and where
a majority vote is taken.
Since the receiver synchronizes itself to frames, the external transmitting and
receiving devices do not have to use a synchronized serial clock. The clock
can be generated locally.
Figure 8–6. SCI Asynchronous Communications Format
Majority
vote
Falling edge
detected
Start bit LSB of data
SCICLK
(internal)
SCIRXD
12345678123456781
8 SCICLK periods per data bit 8 SCICLK periods per data bit
8.4.1 Receiver Signals in Communication Modes
Figure 8–7 illustrates an example of receiver signal timing that assumes the
following conditions:
- Address-bit wake-up mode (address bit does not appear in idle-line mode)
- Six bits per character