Specifications

SCI Multiprocessor Communication
8-10
In both multiprocessor modes, the receipt sequence is:
1) At the receipt of an address block, the SCI port wakes up and requests an
interrupt (bit RX/BK INT ENA-SCICTL2.1 must be enabled to request an
interrupt). It reads the first frame of the block, which contains the destina-
tion address.
2) A software routine is entered through the interrupt and checks the incom-
ing address. This address byte is checked against its device address byte
stored in memory.
3) If the check shows that the block is addressed to the device CPU, the CPU
clears the SLEEP bit and reads the rest of the block; if not, the software
routine exits with the SLEEP bit still set and does not receive interrupts un-
til the next block start.
8.3.1 Idle-Line Multiprocessor Mode
In the Idle-line multiprocessor protocol (ADDR/IDLE MODE bit=0), blocks are
separated by having a longer idle time between the blocks than between
frames in the blocks. An idle time of ten or more high-level bits after a frame
indicates the start of a new block. The time of a single bit is calculated directly
from the baud value (bits per second). The idle-line multiprocessor commu-
nication format is shown in Figure 8–3 (ADDR/IDLE MODE bit is SCICCR.3).
Figure 8–3. Idle-Line Multiprocessor Communication Format
Address Data Last Data
First frame within block
Is address; it follows idle
period of 10 bits or more
Frame within
block
Idle period
less than
10 bits
Idle period
of 10 bits
or more
Several blocks of frames
Data format
(Pins SCIRXD, SCITXD)
Data format expanded
Idle periods of 10 bits or more
separate the blocks
Start
Start Start
One block of frames