Specifications

Differences vs. ’C240 SCI
8-4
Figure 8–1. SCI Block Diagram
SCIRXST.6
SCIRXST.5
Frame format and mode
Parity
Even/odd Enable
SCICCR.6 SCICCR.5
SCICTL1.3
WUT
1
Transmitter data
buffer register
SCITXBUF.7–0
8
SCICTL2.7
SCICTL2.6
SCICTL2.0
SCI TX interrupt
TXRDY TXINTENA
TXEMPTY
TXINT
SCIHBAUD.15–8
Baud rate
MSbyte
register
SCILBAUD.7–0
Baud rate
LSbyte
register
SCI
clock
External
connections
SCICTL1.1
TXENA
SCITXD
SCIRXD
SCI priority level
Low INT priority
High INT priority
1
0
1
0
Low INT priority
High INT priority
SCITX priority
SCIPRI.6
SCIRX priority
SCIPRI.5
RXSHF
register
8
SCICTL1.0
SCIRXST.1
SCICTL1.6
RXWAKE
RXERRINTENA
RX error
SCIRXST.7 SCIRXST.4–2
RX error FE OE PE
Receiver data
buffer register
SCIRXBUF.7–0
RXENA
SCI RX interrupt
RXRDY RX/BKINTENA
BRKDT
RXINT
TXSHF
register
SCICTL2.1