Specifications

8-1
Serial Communications Interface (SCI)
This chapter describes the architecture, functions, and programming of the
serial communications interface (SCI) module. All registers in this peripheral
are eight bits wide.
The programmable SCI supports asynchronous serial (UART) digital commu-
nications between the CPU and other asynchronous peripherals that use the
standard NRZ (non-return-to-zero) format. The SCI’s receiver and transmitter
are double buffered, and each has its own separate enable and interrupt bits.
Both may be operated independently or simultaneously in the full-duplex
mode.
To ensure data integrity, the SCI checks received data for break detection, par-
ity, overrun, and framing errors. The bit rate (baud) is programmable to over
65,000 different speeds through a 16-bit baud-select register.
For convenience, references to a bit in a register are abbreviated using the
register name followed by a period and the number of the bit. For example, the
notation for bit 6 of SCI priority control register (SCIPRI) is SCIPRI.6.
Topic Page
8.1 Differences vs. ’C240 SCI 8-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 SCI Programmable Data Format 8-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3 SCI Multiprocessor Communication 8-9. . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4 SCI Communication Format 8-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5 SCI Port Interrupts 8-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6 SCI Module Registers 8-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 8