Specifications

ADC Conversion Clock Cycles
7-34
7.7 ADC Conversion Clock Cycles
The conversion time is a function of the number of conversions performed in
a given sequence. The conversion cycle can be divided into five phases:
- Start of Sequence Sync-up (SOS_synch)
The SOS_synch applies only to the first conversion in a sequence.
- Acquisition time (ACQ)
- Conversion time (CONV)
- End of Conversion cycle (EOC)
The ACQ, CONV, and EOC apply to all conversions in a sequence
- End of Sequence flag-setting cycle (EOS)
The EOS applies only to the last conversion in a sequence.
Each category is listed in Table 7–7 with the number of CLKOUT cycles it takes
to complete.
Table 7–7. ADC Conversion Phases vs CLKOUT cycles
Conversion phase
CLKOUT cycles
(CPS = 0)
CLKOUT cycles
(CPS = 1)
SOS_synch 2 2 or 3
{
ACQ 2
}
4
}
CONV 10 20
EOC 1 2
EOS
1 1
†
When CPS = 1, a “Start of Sequence” can take an extra CLKOUT cycle to sync up with the ADC
clock (ADCCLK) depending on which cycle the SOC bit is set in software.
‡
The ACQ value is dependent on the ACQ_PSn bits. Values shown in Table 7–7 are applicable
when ACQ_PS = 0. As an example, values for ACQ when ACQ_PS = 1, 2, and 3 are shown
in Table 7–8. This table can be extrapolated for all ACQ_PS values.
Table 7–8. ACQ Values When ACQ_PS = 1, 2, and 3
ACQ_PS (CPS = 0) (CPS = 1)
1 ACQ = 4 ACQ = 8
2 ACQ = 6 ACQ = 12
3
ACQ = 8 ACQ = 16