Specifications

Register Bit Descriptions
7-33 Analog-to-Digital Converter (ADC)
7.6.6 ADC Conversion Result Buffer Registers (for Dual-Sequencer Mode)
RESULT15 8th Conv (Seq 2) 16th Conv
Note: In the cascaded sequencer mode, registers RESULT8 through RESULT15 will hold the
results of the ninth through fifteenth conversions.
Figure 7–12. ADC Conversion Result Buffer Registers
15 14 13 12 11 10 9 8
D9
D8 D7 D6 D5 D4 D3 D2
76543210
D1
D0 0 0 0 0 0 0
Notes: 1) Buffer addresses = 70A8h to 70B7h (i.e., 16 registers)
2) The 10-bit conversion result (D9–D0) is left-justified.