Specifications

Register Bit Descriptions
7-31 Analog-to-Digital Converter (ADC)
7.6.5 ADC Input Channel Select Sequencing Control Registers
Figure 7–11.ADC Input Channel Select Sequencing Control Registers (CHSELSEQn)
Bits 15–12 Bits 11–8 Bits 7–4 Bits 3–0
70A3h CONV03
CONV02 CONV01 CONV00 CHSELSEQ1
RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bits 15–12 Bits 11–8 Bits 7–4 Bits 3–0
70A4h CONV07
CONV06 CONV05 CONV04 CHSELSEQ2
RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bits 15–12 Bits 11–8 Bits 7–4 Bits 3–0
70A5h CONV11
CONV10 CONV09 CONV08 CHSELSEQ3
RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bits 15–12 Bits 11–8 Bits 7–4 Bits 3–0
70A6h CONV15
CONV14 CONV13 CONV12 CHSELSEQ4
RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Each of the 4-bit fields, CONVnn, selects one of the sixteen muxed analog in-
put ADC channels for an autosequenced conversion.