Specifications

Register Bit Descriptions
7-29 Analog-to-Digital Converter (ADC)
Table 7–4. Bit Selections for MAX_CONV1 for Various Number of Conversions
MAX_CONV1.3–0 Number of conversions
0000 1
0001 2
0010 3
0011 4
0100 5
0101 6
0110 7
0111 8
1000 9
1001 10
1010 11
1011 12
1100 13
1101 14
1110 15
1111
16
7.6.4 Autosequence Status Register
Figure 7–10. Autosequence Status Register (AUTO_SEQ_SR) — Address 70A7h
15–12 11 10 9 8
Reserved
SEQ_
CNTR_3
SEQ_
CNTR_2
SEQ_
CNTR_1
SEQ_
CNTR_0
R-x R-0 R-0 R-0 R-0
76543210
SEQ2-
State3
SEQ2-
State2
SEQ2-
State1
SEQ2-
State0
SEQ1-
State3
SEQ1-
State2
SEQ1-
State1
SEQ1-
State0
R-1 R-0 R-0 R-0 R-0 R-0 R-0 R-0
Note: R = Read access, x = undefined, -0 = value after reset
Bits 15–12 Reserved
Bits 11–8 SEQ_CNTR_3 – SEQ_CNTR_0. Sequencing counter status bits
The SEQ_CNTR_n 4-bit status field is used by SEQ1, SEQ2, and the cas-
caded sequencer.