Specifications

Register Bit Descriptions
7-27 Analog-to-Digital Converter (ADC)
Bit 1 INT_FLAG_SEQ2. ADC interrupt flag bit for SEQ2
This bit indicates whether an interrupt event has occurred or not. This bit must
be cleared by the user writing a 1 to it.
0 No interrupt event.
1 An interrupt event has occurred.
Bit 0 EVB_SOC_SEQ2. Event Manager B SOC mask bit for SEQ2
0 SEQ2 cannot be started by EVB trigger.
1 Allows SEQ2 to be started by Event Manager B trigger. The Event
Manager can be programmed to start a conversion on various
events. See chapter 6, Event Manager (EV), for details.
7.6.3 Maximum Conversion Channels Register
Figure 7–9. Maximum Conversion Channels Register (MAX_CONV) — Address 70A2h
15–8
Reserved
R-x
76543210
Reserved
MAX_
CONV2_2
MAX_
CONV2_1
MAX_
CONV2_0
MAX_
CONV1_3
MAX_
CONV1_2
MAX_
CONV1_1
MAX_
CONV1_0
R-x RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, x = undefined, -0 = value after reset
Bits 15–7 Reserved
Bits 6–0 MAX_CONVn. MAX_CONVn bit field defines the maximum number of auto-
conversions. The bit fields and their operation vary according to the sequencer
modes (dual/cascaded). The following table summarizes the differences.
Value SEQ1 SEQ2 Cascaded
Initial state CONV00 CONV08 CONV00
End state CONV07 CONV15 CONV15
Max value 7 7 15
Max value + 1
8 8 16