Specifications

Register Bit Descriptions
7-26
Bit 5 SOC_SEQ2. Start-of-conversion trigger for Sequencer 2 (SEQ2)
(Only applicable in dual-sequencer mode, ignored in cascaded mode.)
This bit can be set by the following triggers:
- S/W – Software writing of 1 to this bit
- EVB – Event Manager B
When a trigger occurs, there are 3 possibilities:
Case 1: SEQ2 idle and SOC bit clear
SEQ2 starts immediately (under arbiter control) and the bit is cleared, allowing
for any “pending” trigger requests.
Case 2: SEQ2 busy and SOC bit clear
Bit is set signifying a trigger request is pending. When SEQ2 finally starts after
completing current conversion, this bit will be cleared.
Case 3: SEQ2 busy and SOC bit set
Any trigger occurring in this case will be ignored (lost).
0 Clears a Pending SOC trigger.
Note: If the sequencer has already started, this bit will automatical-
ly be cleared, and hence, writing a zero will have no effect; i.e., an
already started sequencer cannot be stopped by clearing this bit.
1 Software trigger – Start SEQ2 from currently stopped position (i.e.,
Idle mode)
Bit 4 SEQ2_BSY. SEQ2 Busy
This bit is set to a 1 while the ADC autoconversion sequence is in progress.
It is cleared when the conversion sequence is complete.
0 Sequencer is idle (i.e., waiting for trigger).
1 Conversion sequence is in progress.
Bits 3–2 INT_ENA_SEQ2. Interrupt-mode-enable control for SEQ2
Bit 3 Bit 2 Operation Description
0 0 Interrupt is Disabled
0 1 Interrupt Mode 1
Interrupt requested immediate on INT_FLAG_SEQ2 flag
set
1 0 Interrupt Mode 2
Interrupt requested only if INT_FLAG_SEQ2 flag is al-
ready set. If clear, INT_FLAG_SEQ2 flag is set and INT
request is suppressed. (This mode allows Interrupt re-
quests to be generated for every other EOS)
1
1 Reserved