Specifications

Register Bit Descriptions
7-25 Analog-to-Digital Converter (ADC)
Bit 12 SEQ1_BSY. SEQ1 Busy
This bit is set to a 1 while the ADC autoconversion sequence is in progress.
It is cleared when the conversion sequence is complete.
0 Sequencer is Idle (i.e., waiting for trigger).
1 Conversion sequence is in progress.
Bits 11–10 INT_ENA_SEQ1. Interrupt-mode-enable control for SEQ1
Bit 11 Bit 10 Operation Description
0 0 Interrupt is Disabled
0 1 Interrupt Mode 1
Interrupt requested immediately when INT_FLAG_SEQ1
flag is set
1 0 Interrupt Mode 2
Interrupt requested only if INT_FLAG_SEQ1 flag is al-
ready set. If clear, INT_FLAG_SEQ1 flag is set and INT
request is suppressed. (This mode allows Interrupt re-
quests to be generated for every other EOS.)
1
1 Reserved
Bit 9 INT_FLAG_SEQ1. ADC interrupt flag bit for SEQ1
This bit indicates whether an interrupt event has occurred or not. This bit must
be cleared by the user writing a 1 to it.
0 No interrupt event
1 An interrupt event has occurred.
Bit 8 EVA_SOC_SEQ1. Event Manager A SOC mask bit for SEQ1
0 SEQ1 cannot be started by EVA trigger.
1 Allows SEQ1 to be started by Event Manager A trigger. The Event
Manager can be programmed to start a conversion on various
events. See chapter 6, Event Manager (EV), for details.
Bit 7 EXT_SOC_SEQ1. External signal start-of-conversion bit for SEQ1
0 No action
1 Setting this bit enables an ADC autoconversion sequence to be
started by a signal from the ADCSOC device pin.
Bit 6 RST_SEQ2. Reset SEQ2
0 No action
1 Immediately resets SEQ2 to an initial “pretriggered” state, i.e.,
waiting for a trigger at CONV08. A currently active conversion se-
quence will be aborted.