Specifications

7-24

Bit 14 RST_SEQ1 / STRT_CAL. Reset Sequencer/Start Calibration

Case: Calibration Disabled (Bit 3 of ADCTRL1) = 0

Writing a 1 to this bit will reset the sequencer immediately to an initial “pretrig-

gered” state, i.e., waiting for a trigger at CONV00. A currently active conver-

sion sequence will be aborted.

0 No action

1 Immediately reset sequencer to state CONV00

Case: Calibration Enabled (Bit 3 of ADCTRL1) = 1

Writing a 1 to this bit will begin the converter calibration process.

0 No action

1 Immediately start calibration process

Bit 13 SOC_SEQ1. Start-of-conversion (SOC) trigger for Sequencer 1 (SEQ1). This

bit can be set by the following triggers:

- S/W – Software writing a 1 to this bit

- EVA – Event Manager A

- EVB – Event Manager B (only in cascaded mode)

- EXT – External pin (i.e., the ADCSOC pin)

When a trigger occurs, there are 3 possibilities:

Case 1: SEQ1 idle and SOC bit clear

SEQ1 starts immediately (under arbiter control). This bit is set and cleared, al-

lowing for any “pending” trigger requests.

Case 2: SEQ1 busy and SOC bit clear

Bit is set signifying a trigger request is pending. When SEQ1 finally starts after

completing current conversion, this bit will be cleared.

Case 3: SEQ1 busy and SOC bit set

Any trigger occurring in this case will be ignored (lost).

0 Clears a pending SOC trigger.

Note: If the sequencer has already started, this bit will automatical-

ly be cleared, and hence, writing a zero will have no effect; i.e., an

already started sequencer cannot be stopped by clearing this bit.

1 Software trigger – Start SEQ1 from currently stopped position (i.e.,

Idle mode)