Specifications

7-22

quence is active. This bit will take effect at the end of the current conversion

sequence; i.e., software can set/clear this bit until EOS has occurred, for valid

action to be taken. In the continuous conversion mode, there is no need to re-

set the sequencer; however, the sequencer must be reset in the start-stop

mode to put the converter in state CONV00.

0 Start-stop mode. Sequencer stops after reaching EOS. This is

used for multiple time-sequenced triggers.

1 Continuous conversion mode. After reaching EOS, the sequencer

starts all over again from state CONV00 (for SEQ1 and cascaded)

or CONV08 (for SEQ2).

Bit 5 INT_PRI. ADC interrupt request priority

0 High priority

1 Low priority

Bit 4 SEQ_CASC. Cascaded sequencer operation

This bit determines whether SEQ1 and SEQ2 operate as two 8-state

sequencers or as a single 16-state sequencer (SEQ).

0 Dual-sequencer mode. SEQ1 and SEQ2 operate as two 8-state

sequencers.

1 Cascaded mode. SEQ1 and SEQ2 operate as a single 16-state

sequencer (SEQ).

Bit 3 CAL_ENA. Offset calibration enable

When set to 1, CAL_ENA disables the input channel multiplexer, and connects

the calibration reference selected by the bits HI/LO and BRG_ENA to the ADC

core inputs. The calibration conversion can then be started by setting bit 14

of ADCTRL2 register (STRT_CAL) to 1. Note that CAL_ENA should be set to 1

first before the STRT_CAL bit can be used.

Note: This bit should not be set to 1 if STEST_ENA = 1

0 Calibration mode disabled

1 Calibration mode enabled

Bit 2 BRG_ENA. Bridge enable

Together with the HI/LO bit, BRG_ENA allows a reference voltage to be con-

verted in calibration mode. See the description of the HI/LO bit for reference

voltage selections during calibration.

0 Full reference voltage is applied to the ADC input

1 A reference midpoint voltage is applied to the ADC input