Specifications

Register Bit Descriptions
7-21 Analog-to-Digital Converter (ADC)
Bits 11–8 ACQ_PS3 – ACQ_PS0. Acquisition time window – prescale bits 3–0
These bits define the ADC clock prescale factor applied to the acquisition por-
tion of the conversion. The prescale values are defined below:
ACQ
ACQ
ACQ
ACQ
Pre-
l
Acquisition
Ti
Source Z
(CPS 0)
Source Z
(CPS 1)
#
ACQ_
PS3
ACQ_
PS2
ACQ_
PS1
ACQ_
PS0
scaler
(div by)
Time
Window
(CPS=0)
(Ω)
(CPS=1)
(Ω)
0
0 0 0 0 1 2 x T
clk
67 385
10001 2 4 x T
clk
385 1020
20010 3 6 x T
clk
702 1655
30011 4 8 x T
clk
1020 2290
40100 510 x T
clk
1337 2925
50101 612 x T
clk
1655 3560
60110 714 x T
clk
1972 4194
70111 816 x T
clk
2290 4829
81000 918 x T
clk
2607 5464
910011020 x T
clk
2925 6099
A10101122 x T
clk
3242 6734
B10111224 x T
clk
3560 7369
C11001326 x T
clk
3877 8004
D11011428 x T
clk
4194 8639
E11101530 x T
clk
4512 9274
F
1 1 1 1 16 32 x T
clk
4829 9909
Notes: 1) Period of T
clk
is dependent on the “Conversion Clock Prescale” bit (Bit 7); i.e.,
CPS = 0: T
clk
= 1/CLK (for example, for CLK = 30 MHz, T
clk
= 33 ns)
CPS = 1: T
clk
= 2 × (1/CLK) (for example, for CLK = 30 MHz, T
clk
= 66 ns)
2) Source impedance Z is a design estimate only.
Bit 7 CPS. Conversion clock prescale
This bit defines the ADC conversion logic clock prescale
0F
clk
= CLK/1
1F
clk
= CLK/2
CLK = CPU clock frequency
Bit 6 CONT_RUN. Continuous run
This bit determines whether the sequencer operates in continuous conversion
mode or start-stop mode. This bit can be written while a current conversion se-